Current methods for fabricating silicon-on-insulator (SOI) semiconductor devices involve a complex fusion bonding process that includes many fabrication steps prior to the actual fusion bonding. Some of these steps include masking, deposition, and etching. More specifically, current SOI fabrication methods require that a piezoresistive pattern be defined within the semiconductor substrate before fusion bonding. Patterning before fusion bonding, however, limits fabrication design as the final piezoresistive design must be selected during the early processes of fabrication, which results in less than ideal yields and increased wafer processing costs.
For illustrative examples, reference is made to U.S. Pat. No. 5,286,671, entitled “FUSION BONDING TECHNIQUE FOR USE IN FABRICATING SEMICONDUCTOR DEVICES”, issued Feb. 15, 1994 and U.S. Pat. No. 7,439,159, entitled “FUSION BONDING PROCESS AND STRUCTURE FOR FABRICATING SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR DEVICES”, issued Oct. 21, 2008, to A. D. Kurtz et. al., both of which assigned to the assignee hereof, Kulite Semiconductor Products, Inc. The entire disclosures of which are hereby incorporated by reference as if being set forth in their entirety herein.
The present invention describes an improved fusion bonding process for fabricating SOI semiconductor devices, wherein the piezoresistive pattern may be defined after fusion bonding, which therefore provides more versatility in SOI fabrication and cheaper manufacturing costs.